1. Field of the Invention
The invention relates to an interface circuit, and particularly to an interface circuit between a CD-ROM (Compact Disc-Read Only Memory) drive device and a computer.
2. Related Art
As a system for conducting data input/output operations between a computer and a peripheral device, known is the DMA (Direct Memory Access) method in which a microprocessor controls only the start and end of the input/output operations, and a DMA controller (hereinafter, referred to as merely "controller") controls the data transfer between a memory and the peripheral device, thereby performing a high speed data transfer.
FIG. 4 is a diagram showing an example of a data transfer in the conventional art which is conducted by the DMA method through an interface circuit (hereinafter, referred to as "I/F card"). In the figure, 1 designates an 8-bit computer, 2 designates an I/F card which is detachably mounted in the computer 1, and 3 designates a CD-ROM drive device (hereinafter, referred to as merely "drive device") which is a peripheral device.
The drive device 3 has a well known configuration in which a digital signal processing circuit for improving the error correction facility is added to a conventional CD (Compact Disc) player for reproducing music, and reproduces 16-bit digital data recorded on a CD-ROM disc and having the same frame structure as that of a compact disc.
Each 16-bit digital data is recorded on a CD-ROM disc after it is converted into two 8-bit symbols and each of the symbols undergoes the EFM modulation to be converted into two 14-bit symbols having a predetermined frame structure to which error correction codes, etc. are added. The drive device 3 reads data from the CD-ROM disc and conducts a predetermined signal process on the readout data, and the data are transferred in 8-bit units to the computer 1 as shown in FIG. 5.
Specifically, when the I/F card 2 receives a DRQ (DMA Request) signal (FIG. 5(A)) from the drive device 3, the I/F card outputs the signal to the computer 1. In response to this, a controller in the computer 1 sends a memory bus (hereinafter, referred to as merely "bus") enable request to a microprocessor. As soon as the memory access process of the microprocessor is completed, the microprocessor gives a bus enable to the controller.
When the bus enable is given to the controller, a DAC (DMA Acknowledge) signal (FIG. 5(B)) is output to the I/F card 2 which in turn sends this signal to the drive device 3 to notify the bus enable. Similarly, an IOR (I/O Read) signal (FIG. 5(C)) which is a read control signal for controlling the timing of the data transfer is output to the drive device 3 through the I/F card 2.
A command DA which instructs the drive device 3 to output data in accordance with the IOR signal when it receives the DAC signal and the IOR signal is previously input to the drive device 3 through the I/F card 2. Accordingly, upper 8 bits (D.sub.1) and lower 8 bits (D.sub.2) of data reproduced by the drive device 3 are alternatingly output to the I/F card 2 (FIG. 5(D)) during the low-level period of the IOR signal. Similarly, the I/F card 2 transfers these data in an alternating manner to the computer 1.
In the conventional I/F card described above, 8-bit data output from the drive device are transferred to the computer in accordance with the IOR signal, and the controller controls the transfer so that the direct memory access is conducted on the memory of the computer, thereby achieving a high speed transfer. This produces a problem in that it is not possible to conduct the data transfer between, for example, a 16-bit computer and the drive device.
Moreover, it has been desired to conduct the data transfer from various peripheral devices including a drive device at a higher speed to allow a microprocessor to use a bus for a longer period, so that a computer has an advanced function and operates at a high speed.